1. Technical Field
The subject matter disclosed herein is related generally to semiconductor structures. More particularly, the subject matter disclosed herein relates to a method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof.
2. Related Art
The layers of material forming a semiconductor structure undergo a variety of physical changes during the formation of the semiconductor structure. For example, during a metal annealing process, the metal layers of the semiconductor structure may be exposed to high temperatures for an extended period of time, and may also experience a compression force from the layers of the semiconductor positioned above the metal layers. Due to the high temperature and/or compression force, some of the metal layers of the semiconductor structure may form extrusions during the metal annealing process. These extrusions may form on the sidewalls of the semiconductor structure, and may result in shorting of an active circuit area within the semiconductor structure.
Conventional semiconductor structures may include a slot or void in a metal layer surrounding the active circuit area to compensate for anticipated extrusions formed during the metal annealing process. However, dependent on the exposure to the high temperature during the metal annealing process, the metal layer may still form extrusions that short the active circuit area. That is, the slots or voids may not prevent shorting in the circuit, especially in the semiconductor structure which includes a small island circuit (e.g., metal-insulator-metal capacitor). The extrusions may be controlled by making the slots or voids larger. However, by making the slots or voids larger, the size of the active circuit becomes larger, which results in a larger semiconductor structure. Electronic devices utilizing a larger semiconductor structure may require new design of the circuitry and/or may require a larger overall size, which is undesirable.